1. Field of the Invention
This invention relates to an error correction device, an error correction program and an error correction method for correcting one or more than one errors that appear in received data.
2. Description of the Related Art
The data that are exchanged between apparatus can become error data as noises get mixed with the data. Then, the errors are corrected by means of an error correcting code. Error corrections performed by error correction devices can be sorted into those that involve erasure and those that do not involve any erasure.
An error correction device in a disk drive will be described below as an example of error correction device. Erasure information includes information on TAs (thermal asperities: error signals produced by temperature) and code violations from the RDC (read channel) and information given from the MPU (micro processing unit). Erasure information is given before the start of an error-correcting operation and, when erasure is involved, the software of the MPU or the like intervenes in the error-correcting operation. In the error-correcting operation, if an error-correcting code can maximally correct t errors when erasure is not involved, it can maximally correct t×2 errors when erasure is involved.
Firstly, correction of errors that do not involve erasure will be described. FIG. 4 of the accompanying drawings is a conceptual illustration of a known error correction device for errors that do not involve erasure and the flow of the operation of the device. As shown in FIG. 4, with an error correction device for errors that do not involve erasure, the RDC 22 generates a reception word by converting the analog signal from the data storage disk 21 into a 10-bit digital signal. Additionally, the RDC 22 inputs the reception word to the error-correcting circuit 23a for errors that do not involve erasure of the hard disk controller 23 for error correction. Note that the error-correcting circuit 23a for errors that do not involve erasure is formed by hardware.
The error-correcting circuit 23a for errors that do not involve erasure executes an error-correcting operation in the following sequence. Firstly, the error-correcting circuit 23a for errors that do not involve erasure generates a syndrome that gives a cue for error correction from the reception word received from the RDC 22 (Step S21). Then, the error-correcting circuit 23a for errors that do not involve erasure carries out the computation of an error locator polynomial and an error evaluator polynomial according to the generated syndrome (Step S22). Thereafter, the error-correcting circuit 23a for errors that do not involve erasure computationally determines the error positions and the error values by Chien search, using the two polynomials including the error locator polynomial and the error evaluator polynomial (Step S23).
Then, the error-correcting circuit 23a for errors that do not involve erasure performs an error-correcting operation on the reception word according to the error positions and the error values that are computationally determined and writes the outcome of the operation in the RAM (random access memory) 23b (Step S24). All the operations of the above Step S21 through S24 are carried out by hardware. As the error-correcting process is executed by hardware, the processing time required for the error correction is short.
Now, correction of errors that involve erasure will be described below. FIG. 5 of the accompanying drawings is a conceptual illustration of a known error correction device for errors that involve erasure and the flow of the operation of the device. As shown in FIG. 5, with an error correction device for errors that involve erasure, the RDC 22 generates a reception word by converting the analog signal from the data storage disk 21 into a 10-bit digital signal and, at the same time, detects erasure in the reception word to generate erasure information. Then, the RDC 22 inputs the reception word and the erasure information to the error-correcting circuit 23a for errors that involves erasure of the hard disk controller 23. A circuit same as the error-correcting circuit 23a for errors that do not involve erasure of the error correction device for errors that do not involve erasure as illustrated in FIG. 4 is used in the error correction device for errors that involve erasure shown in FIG. 5.
In the error correction device for errors that involve erasure illustrated in FIG. 5, while the error correcting-circuit 23a for errors that do not involve erasure of the hard disk controller 23 receives erasure information and a reception word from the RDC 22, generates a syndrome and holds the erasure information (Step S31), it does not have the functional feature of executing a step of carrying out the computation of an error locator polynomial and an error evaluator polynomial (corresponding to Step S22 in FIG. 4), a step of computationally determining the error positions and the error values by Chien search (corresponding to Step S23 in FIG. 4) and a step of performing an error-correcting operation on the reception word (corresponding to Step S24 in FIG. 4). Since correction of errors that involve erasure requires a huge circuit if it is to be performed by means of hardware, it is necessary to provide an MPU 24 that is dedicated to execution of a program designed only for an error-correcting process of correcting errors that involve erasure as shown in FIG. 5.
Thus, the operation of correcting errors that involve erasure to be performed by an error correction device for errors that involve erasure follows the sequence as described below. Firstly, as described above, the error-correcting circuit 23a for errors that do not involve erasure of the hard disk controller 23 receives erasure information and a reception word from the RDC 22 and holds the erasure information (Step S31). Then, the MPU 24 dedicated to an error-correcting process of correcting errors that involve erasure acquires the syndrome and the erasure information from the error-correcting circuit 23a for errors that do not involve erasure (Step S32) and carries out the computation of an error locator polynomial and an error evaluator polynomial according to the syndrome and the erasure information (Step S33). Additionally, the MPU 24 computationally determines the error positions and the error values for errors that involve erasure by Chien search, using the two polynomials including the error locator polynomial and the error evaluator polynomial (Step S34). Then, the MPU 24 carries out an error-correcting operation on the reception word and writes the outcome of the operation in the RAM 13b (Step S35). Note that Step S34 (of computationally determining the error positions and the error values by Chien search) and Step S35 (of correcting errors) do not discriminate errors involving erasure and other errors and hence are applied to all errors.
For correction of errors that involve erasure, the error-correcting circuit 23a for errors that do not involve erasure (which is hardware) is only responsible for Step S31 of generating a syndrome and holding erasure information whereas the MPU 24 (which is software) is responsible for the steps from Step S32 of acquiring the syndrome and the erasure information to the Step S35 of carrying out an error-correcting operation. In this way, hardware and software share the responsibility of correcting errors that involve erasure.
The prior art that relates to the present invention includes the technique disclosed in Patent Document 1 [Jpn. Pat. Appln. Laid-Open Publication No. 2001-101020 (see Paragraphs 0137 through 0138 and FIG. 1)]. With the disclosed technique, it is possible to carry out an error-correcting operation of correcting errors that involve erasure at high speed, while minimizing the increase of the circuit size of the hardware, by using an MPU for correction of errors of erased data.
However, for correction of errors that involve erasure, when the MPU 24, which is software, corrects errors that involve erasure by Chien search in Step S34 of FIG. 5, it has to check all the data positions where an error can take place to see if each of the data positions is actually an error position or not. This checking operation requires a long processing time. In other words, since Chien search operation is conducted for all the data positions by means of software like a round robin event, it takes a long time to carry out the Chien search operation and computationally determines all the error positions and all the error values, including those involving erasure. As a result, the process of correcting errors involving erasure entails a long processing time.